By Rodnay Zaks
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Additional resources for 6502 Applications Book
Technique I In order to identify quickly which one of four devices has requested service, a sequential table access technique may be used, provided the addresses of the 4 devices are sequential in the memory. Address n will be allocated to CRAl, address n + 1 to CRBl, address n + 2 to CRA2, address n + 3 to CRB3, etc. The program can then make use of the indexed indirect addressing feature and is shown below: START NEXT LOX LOA BMI DEX BEQ BNE 28 #8 (BASE-1,X) SERVICE START NEXT INDEX ACCESS NEXT CR IRQON?
I I I CA2 Output High Mode-The CA2 output is held high in this mode. Mode Fig. 2-24: PCR Detalled Operation (courtesy: Rockwell) PCR7 PCR6 PCRS Mode 0 0 0 CB2 Negative Edge Interrupt (IF3/0RB Clear) Mode-Set CB2 interrupt flag (IFR3) on a negative transition of the CB2 input signal. Clear IFR3 on a read or write of the Peripheral B Output Register (ORB) or by writing logic I into IFR3. 0 0 I CB2 Negative Edge Interrupt (IFR3 Clear) Mode-Set IFR3 on a negative transition of the CB2 input signal.
I 0 0 Free-running output at rate determined by Timer 2. 1 0 1 Shift out under control of Timer 2. I 1 0 Shift out under control of the 02 pulses. 1 I I Shift out under control of external clock pulses. Fig. 2-33 Shift Register Control On output, the user will load the shift register. This will automatically start the timing and shifting process. Whenever 8 bits will have been shifted out of the register, the interrupt flag (bit 2 of the interrupt flag register) will be set automatically. It can then be tested by the program.
6502 Applications Book by Rodnay Zaks